XC2S200E-6PQ208C

Field-Programmable Gate Array, –0.5 to 2.0 V, Very low cost, QFP-208, Unlimited in-system reprogrammability

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Price:: US $6.40~7.00 / piece [Get Latest Price]

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	US $6.40~7.00

PartNumber:: XC2S200E-6PQ208C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Total Price:: US $0

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Products Upload time: 2011-10-09

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Part Number:XC2S200E-6PQ208C
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Product Summary

The XC2S200E-6PQ208C is a 1.8V Field-Programmable Gate Array. The device gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S200E-6PQ208C offers densities ranging from 50,000 to 300,000 system gates. The XC2S200E-6PQ208C delivers more gates, I/Os, and features per dollar by combining advanced process technology with a streamlined architecture based on the proven Virtex-E platform. Features of the XC2S200E-6PQ208C include block RAM (to 64K bits), distributed RAM (to 98,304 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops).

Parametrics

XC2S200E-6PQ208C absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 2.0 V; (2)VCCO, Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 4.0 V; (4)VIN, Input voltage relative to GND: –0.5 to 4.0 V; (5)VTS, Voltage applied to 3-state output:–0.5 to 4.0 V; (6)TSTG, Storage temperature (ambient) –65 to +150℃; (7)TJ, Junction temperature: +125℃.

Features

XC2S200E-6PQ208C features: (1)Densities as high as 6,912 logic cells with up to 300,000 system gates; (2)Streamlined features based on Virtex-E architecture; (3)Unlimited in-system reprogrammability; (4)Very low cost; (5)Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant; (6)Low-power segmented routing architecture; (7)Full readback ability for verification/observability; (8)Dedicated carry logic for high-speed arithmetic; (9)Efficient multiplier support; (10)Cascade chain for wide-input functions; (11)Abundant registers/latches with enable, set, reset; (12)Four dedicated DLLs for advanced clock control; (13)Four primary low-skew global clock distribution nets; (14)IEEE 1149.1 compatible boundary scan logic.